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Answer (Detailed Solution Below)

Option 2 : J = K = 1 and the clock pulse is wider than the flip-flop's propagation delay / J = K = 1 हो और clock pulse फ्लिप-फ्लॉप के propagation delay से चौड़ी हो

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Detailed Solution

सही उत्तर J = K = 1 and the clock pulse is wider than the flip-flop's propagation delay / J = K = 1 हो और clock pulse फ्लिप-फ्लॉप के propagation delay से चौड़ी हो है।

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Question:

The race-around condition in a JK flip-flop occurs when — / JK फ्लिप-फ्लॉप में race-around condition कब उत्पन्न होती है —

1.
J = K = 0 while the clock is high / clock high होने पर J = K = 0 हो
2.
J = K = 1 and the clock pulse is wider than the flip-flop's propagation delay / J = K = 1 हो और clock pulse फ्लिप-फ्लॉप के propagation delay से चौड़ी हो
3.
J = 1, K = 0 during the falling clock edge / falling clock edge पर J = 1, K = 0 हो
4.
the asynchronous preset input is asserted / asynchronous preset input सक्रिय हो

Correct Answer: J = K = 1 and the clock pulse is wider than the flip-flop's propagation delay / J = K = 1 हो और clock pulse फ्लिप-फ्लॉप के propagation delay से चौड़ी हो

With J = K = 1 the output toggles; if the clock stays high longer than the propagation delay, the output toggles multiple times within a single pulse — the race-around condition. / J = K = 1 होने पर output toggle करता है; यदि clock, propagation delay से अधिक समय तक high रहे तो एक ही pulse में output कई बार toggle करता है — यही race-around condition है।

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